A plain-language guide to DC-link capacitor ripple current in a three-phase inverter: the Kolar & Round closed-form expression, why ripple peaks near modulation index 0.6, and what actually sizes the capacitor.
In a three-phase inverter, the switches chop the DC bus into PWM pulses at the switching frequency. That switching draws a violently pulsating current from the DC side, but the battery (through its cabling inductance) can't supply a fast-changing current cleanly. The DC-link capacitor bridges the gap: it sources and sinks the high-frequency ripple current locally, so the bus voltage stays stiff and the pulses don't propagate back up the cable. Sizing that capacitor is really about two things — the ripple current it has to carry (which drives heating and life) and the peak voltage it must withstand.
The hard part is knowing how much RMS ripple current the capacitor actually sees, because it depends on the operating point: the load current, the power factor, and the modulation index (how deep the PWM is driving toward full output). Kolar & Round published a closed-form expression for exactly this (IEE Proc. Electr. Power Appl., 2006) — the RMS DC-link capacitor current for a three-phase voltage-source PWM inverter with sinusoidal output current and a constant DC-link voltage. It replaces a full switching simulation with one equation.
The key result to carry in your head: the ripple current peaks near a modulation index of M ≈ 0.6, at roughly 0.6–0.65 × the RMS phase current. So the worst case for capacitor heating isn't at full modulation — it's partway up. Sizing for full-modulation ripple alone can under-size the capacitor for the operating point that actually cooks it.
A film DC-link capacitor's rated voltage is a peak limit for the (non-reversing) DC waveform — datasheets state the peak voltage must not exceed the rated voltage. So the governing voltage isn't the DC bus alone, it's:
V_peak = V_bus + ½·ΔV_pp
the bus plus half the peak-to-peak ripple. The ripple pushes the required voltage rating up. Two more effects tighten it: above ~85 °C the permissible voltage derates (down to roughly 0.7× rated at 105 °C), and a fast switching turn-off adds a repetitive overshoot spike (ΔV = L_loop·di/dt) on top — which, because it repeats every cycle, also has to stay inside the rating.
The required capacitance is the larger of two constraints:
C = I_C,rms / (2π·f_sw·V_rip,rms)).C ≥ 1 / (L_cable·(2π·f_sw)²)), so the harness doesn't ring.Where the ripple actually peaks across modulation index, how ESR turns ripple into a hot-spot temperature and a lifetime, and a checklist for specifying a DC-link bank.
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