Engineering CalculatorsDC-Link Capacitor Sizing
Size the DC-link capacitor bank for a three-phase motor inverter — from the system operating point to a required capacitance and RMS ripple current (Kolar & Round), then down-select a polypropylene film capacitor (Kemet C4AQ-M or custom), compute loss, hot-spot temperature and expected life, and lay out the parallel bank with array thermal derating.
| Grid | 3 rows × 3 cols (8 caps, last row 2) |
| Envelope W × D × H | 132 × 111 × 46 mm |
| Worst-case cap cooling | 2.6 of 5 faces exposed → Rth ×1.92 |
| Bank ESR / ESL | 0.225 mΩ / 1.6 nH (N in parallel; interconnect/busbar adds to ESL) |
| Estimated bank mass | 730 g (0.73 kg) ≈ box volume × 1.35 g/cm³ |
| Total stored energy | 51.2 J |
| di/dt | 9,433 A/µs (9.4 kA/µs) |
| Commutation-loop inductance | 30 nH |
| Device-side overshoot ΔV | 283 V → peak 683 V (vs your switch rating) |
| Cap-terminal peak (repetitive) | 419 V = bus + ½ ripple + 15 V ESL spike · rating 500 V |
New to DC-Link Ripple? Read the guide: DC-Link Capacitor Ripple: The Kolar & Round Method — a plain-language explainer of the standard behind this calculator.
Voltage rating: the capacitor's rated voltage is a PEAK limit for the (non-reversing) DC-link waveform — the KEMET datasheet states "the peak voltage shall not exceed the rated voltage VNDC," and TDK defines its rated voltage as the maximum operating peak voltage. So the governing voltage is V_peak = V_bus + ½·ΔV_pp (the ripple pushes the required rating up, not just the DC bus), and above 85 °C the permissible voltage derates below the rating (linear to ~0.7×V_rated at 105 °C). Occasional surges to ~1.5×V_rated are allowed (limited cycles), but continuous operation at ≤0.8×V_rated greatly extends life. Bank mass is estimated from the box envelope volume at an effective packaged density of 1.35 g/cm³ (film + resin + box + terminals) — an approximation; use the datasheet weight for precise figures. Bank ESR and ESL are the N-in-parallel combinations of the per-part values; real bank ESL is dominated by the busbar/interconnect layout, which is not included. Switching overshoot uses ΔV = L_loop·di/dt: the commutation-loop inductance (entered, or estimated from a laminated busbar as µ₀·separation·length/width plus the module and cap-bank ESL) times the turn-off current slew (from the commutated current and fall time, or entered directly). The device sees the full loop spike (compare against the switch's rating — out of scope here); the capacitor sees only the ESL_bank·di/dt portion added to the DC bus and ripple, and because it repeats every cycle it must stay within the rated voltage. This is a first-order lumped estimate — real overshoot also depends on damping, gate drive and ringing. The DC-link RMS ripple current uses the Kolar & Round closed-form expression (IEE Proc. Electr. Power Appl., 2006, Eq. 28) for a three-phase voltage-source PWM inverter with sinusoidal output current and a constant DC-link voltage; it peaks near modulation index M ≈ 0.6 at roughly 0.6–0.65 × the RMS phase current. The sizing capacitance is the larger of two constraints: the switching-ripple-voltage limit (treating the capacitor reactance as the dominant impedance at f_sw, so C = I_C,rms/(2π·f_sw·V_rip,rms) with V_rip,rms = ΔV_pp/(2√2) — conservative, since all the ripple is taken at the switching frequency), and the source-decoupling minimum C ≥ 1/(L_cable·(2π·f_sw)²) that keeps the cable-inductance/capacitor resonance below the switching frequency. Capacitor loss is P = ESR·I² with the ripple current shared equally across the parallel bank; the hot-spot temperature is ΔT = ESR·I²·R_th (per the KEMET C4AQ-M datasheet), with the single-part R_th derated for the most-enclosed capacitor by its exposed-face fraction (top face plus side faces, side faces facing a neighbour across the gap cooling only partially) and a cooling-method factor (natural / forced air / conduction). ESR is frequency- and temperature-dependent — the datasheet 10 kHz / 70 °C value is used, so real losses vary with the actual ripple spectrum. Expected life uses a PP-film model anchored to the C4AQ-M datasheet — 120,000 h at rated voltage at 70 °C hot spot, halving every ~15 °C (60,000 h at 85 °C), with a (V_rated/V_applied)^7 voltage-acceleration factor — and is a first-order estimate; the manufacturer's lifetime curve for the specific series governs. Capacitor parameters are transcribed from the manufacturer datasheets — KEMET C4AQ-M (F3125), KEMET C4AE (F3046) and TDK/EPCOS B3277x MKP DC-Link (MKP_B32774XYZ_778XYZ). Note the Irms rating basis differs by manufacturer: KEMET quotes the current for a 30 °C hot-spot rise, TDK for a 15 °C rise; the TDK parts' R_th is derived from R_th = ΔT/(ESR·Irms²) with ΔT = 15 °C (which cross-checks against KEMET for matching case sizes). The voltage-derating and life models are generic PP-film approximations. Verify against the current datasheets and, for critical designs, by test.
Validated: the Kolar & Round ripple-current formula was independently re-derived and matched exactly, and sweeping the modulation index at unity power factor confirms the well-known published characteristic stated above — the ratio peaks at M = 0.615 with a value of 0.650, right in the documented "M ≈ 0.6, ~0.6–0.65×" range. LC resonance, both capacitance-sizing constraints, stored energy, busbar loop inductance, and the di/dt and overshoot formulas all matched independent hand calculation exactly.