Why inverter loss is worth getting right

The losses in a traction inverter's power devices set two things that dominate an EV powertrain's design: the efficiency (range) and the cooling (how big and heavy the heatsink and coolant loop have to be). Getting the loss estimate right early tells you whether a given SiC device, paralleling, and switching frequency will stay inside its junction-temperature limit — or cook. The losses split into a few distinct mechanisms, each with its own scaling.

Conduction loss

When a SiC MOSFET is on, it behaves like a resistor: it drops I·R_ds(on) and dissipates I²·R_ds(on). Two things to respect. First, R_ds(on) rises significantly with junction temperature, so conduction loss and temperature chase each other and you have to iterate. Second, running synchronous rectification (the normal way to run SiC — channel conducts in both directions instead of the body diode) makes the total conduction loss symmetric between motoring and generating; the motor/generator distinction only shows up explicitly when sync rect is off and the body diode carries part of the current.

Switching loss

Every turn-on and turn-off dissipates a packet of energy while voltage and current overlap during the transition. Datasheets give these as Eon/Eoff at a test point, and they scale two ways: linearly with the switched current, and with voltage by (V_dc / V_test)^kv. Total switching loss is that energy times the switching frequency — which is why raising f_sw for smaller passives directly buys you more switching loss. A useful SiC fact: Eon/Eoff barely change with junction temperature (unlike silicon IGBTs), so they're treated as temperature-independent.

Reverse-recovery loss

When the opposing device turns on, it has to sweep out the charge stored in the freewheeling device's diode — reverse recovery. SiC's big advantage over silicon is how small this is. It's taken from the datasheet Err where published, or approximated as Q_rr·V_dc / 4 for a soft-recovery device.

What doesn't heat the die

Gate-drive loss is real power, but it's dissipated in the driver and gate resistors, not the silicon — so it's excluded from the junction-temperature solve (though it still matters for the gate-drive supply budget).

The junction-temperature loop & sizing checklist

How conduction, switching and recovery losses feed a thermal solve that chases its own tail, what paralleling and switching frequency do, and a checklist for sizing a SiC inverter stage.

The loss ↔ temperature loop

Total device loss = conduction + switching + reverse recovery. That power times the junction-to-case (and case-to-coolant) thermal resistance gives the junction temperature rise above coolant. But conduction loss depends on R_ds(on), which depends on that very temperature — so the solve iterates: guess a temperature, compute losses, get a new temperature, repeat until it settles. If it settles below the device's T_vj,max with margin, the design is thermally viable; if it runs away, you need a bigger device, more parallel devices, lower f_sw, or better cooling.

The levers

  • Paralleling devices — splits the current, cutting conduction loss per device roughly with the square of the count; the main way to raise current capability.
  • Switching frequency — trades directly against switching loss; higher f_sw shrinks the DC-link cap and filter but heats the devices.
  • Operating point — the worst case for the devices isn't always peak power; check across the drive cycle.

Checklist

  1. Sum conduction (I²·R_ds(on), temperature-dependent), switching (Eon/Eoff × f_sw, current- and voltage-scaled), and reverse-recovery loss.
  2. Iterate the junction temperature until R_ds(on) and losses are self-consistent.
  3. Confirm the settled T_vj is below the datasheet maximum with margin, at the worst operating point.
  4. Use paralleling and/or f_sw to bring it in range; re-check the DC-link and filter impact of any f_sw change.
  5. Transcribe real datasheet loss parameters before trusting absolute numbers — verify critical designs by double-pulse and calorimetric test.

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